Fault emulation: reconfigurable hardware based fault simulation using logic emulation systems with optimized mapping

Reza Sedaghat Maman Fault Emulation: Reconfigurable Hardware-Based Fault Simulation Using Logic Emulation Systems with Optimized Mapping Various approaches to test vector evaluation exist for ascertaining the effectiveness of a test vector set for a specific fault model by computing the ratio between the number of faults detected by this set and the number of modeled faults. The traditional approach to test vector evaluation is software-based, utilizing programs to simulate the effects of the faults on circuit behavior. The simplest method, serial fault simulation, simulates faulty circuits one at a time. In the recent past, more advanced approaches to fault simulation have been proposed and can be categorized, in general, as either parallel or concurrent. These differ from serial fault simulation in their effort to minimize the number of simulation passes by processing faults or test vectors simultaneously. However, the circuit elements must still be processed sequentially in order to simulate the complete circuit. The fault simulation approach is becoming increasingly impractical nowadays, not only because the runtime for simulating one test vector increases linearly to quadratically with the number of circuit elements, but also because circuit complexity increases faster than computing speed. A new approach to fault simulation involves the use of a hardware logic emulator. Logic emulation represents a new method of design validation utilizing a reprogrammable prototype of a digital circuit. In contrast to fault simulation, all circuit elements can be emulated in parallel by the emulation hardware. Therefore, emulation runtime is based solely on the number of faults, which of course also depends on circuit size, and the number of test vectors. Emulation runtime increases only linearly with circuit size making it possible to attain a speedup over software fault simulation. With the goal of satisfying the requirements of rapid fault injection including fault activation, emulator technology independence, optimal fault emulation runtime, minimal hardware overhead, and optimized mapping into reconfigurable hardware, two approaches to fault emulation, FES/1 and FES/2, were developed and implemented. Both approaches use identical methods of fault injection and fault activation in the FPGAs. However, FES/1 uses the so-called in-circuit mode of the emulator, in which test generation and emulation analysis are made feasible through the expansion of the logic emulator by additional hardware modules. FES/2, in contrast, operates in emulator acceleration mode and does not require additional hardware for test vector evaluation. An objective of hardware-based fault injection is the reduction of the FPGA overhead, which results from the fault emulation mapping procedure. This method of fault injection includes mapping the faulty circuit for an optimized partitioning, technology mapping, and placement and routing. The Delta-Path algorithm was developed and utilized in the course of this research for the node assignment optimization problem. The problem is described here as a quadratic assignment problem and its solution using the Delta-path algorithm results in a reduction in FPGA overhead through an improved usage of FPGA resources. In contrast to previously published fault emulation approaches, FES/1 and FES/2 use additional logic functions for fault injection and decoders for fault activation. Faster fault injection is feasible without reconfiguration of the emulator hardware and without dependency on a specific logic emulator technology. In addition, the dependability of a system can be evaluated using a logic emulator for hardwarebased fault injection. Real time fault injection into a target system hardware is an important application of fault emulation for the evaluation of system behavior and involves fault injection into the system for the identification of dependability deficiencies of the system, the observation of system behavior with the given faults, as well as the determination of the degree of fault coverage.